One of the major concerns in semiconductor processing, and in particular, to microminiaturization of CMOS technology, is reduction in coupling capacitance between interconnects in order to limit propagation delay and signal faults due to cross-talk. In order to achieve this goal in reducing the cross-talk between lines, low k-dielectric materials have been increasingly investigated for integration into the interconnect level. However, extreme low k materials have been considered to cause serious integration and reliability problems. In response, it has been suggested to create air gaps in the dielectric material between metal lines, since air has the lowest permittivity that can be achieved. This makes the resulting dielectric constant of the insulating layer to be very low. FIGS. 1–3 depict a prior art process for forming air gaps in the dielectric layer of an interconnect level.
In FIG. 1, a sacrificial interlevel dielectric layer 12 is formed on a substrate 10. Substrate 10 can be any underlying layer or layers, such as another metallization level. Within the ILD layer 12 are recesses in which metal lines 14 are formed. For example, the metal lines 14 may be made of copper, either deposited by electroplating or electroless deposition. A barrier layer 16, consisting of titanium nitride or tantalum nitride, for example, lines the recess and prevents contamination of the dielectric layer by diffusion of copper 14. A conventional material for use as a dielectric material is silicon oxide (SiO2).
In order to create air gaps between the metal lines 14 and reduce the dielectric constant k for a metallization level, an etch back process is performed. This involves etching of the silicon oxide of the dielectric layer 12. However, the etching process would undesirably cause the copper at the top of the metal lines 14 to be sputtered during the etching process if left unprotected. The surface of the metal lines 14 would then undesirably roughen, leading to poor connectivity and increased resistance between metallization levels. Hence, an additional mask set is formed and lithography process steps are performed to create photoresist masks 20 that need to be precisely aligned over the metal lines 14.
FIG. 2 depicts the formation of FIG. 1 following the etching back of the dielectric layer 12. An imprecise alignment of the photoresist masks 20 over the metal lines 14 is depicted to illustrate concerns regarding the problems related to exposure of the copper during etching. This includes copper sputtering around during the process and the roughening of the surface of the copper of the metal lines. Part of the cause of the sputtering of the copper is the relatively high power required to break the strong silicon-oxygen bonding required to etch back the silicon oxide of the dielectric layer 12.
FIG. 3 depicts the structure of FIG. 2 at a non-conformal deposition of silicon oxide (SiO2) over the metal lines 14 and the substrate 10. This forms a second dielectric layer 22. In the narrow space between metal lines 14, the non-conformal deposition of the silicon oxide creates air gaps 24 in the second dielectric layer 22. These air gaps reduce the overall dielectric constant of the second dielectric layer 22. The morphology of the air gaps depends upon the aspect ratio of the trenches and on the step coverage of the process used to achieve the non-conformal dielectric deposition.
The conventional process depicted in FIGS. 1–3 has the disadvantage of requiring an extra mask set and additional lithography steps to create the masks that protect the copper at the top of the metal lines 14. Such protection, however, is essential due to the high power needed to etch back the silicon oxide used as the sacrificial material in the first dielectric layer 12. Otherwise, exposure of copper to the etch process caused by even minimal misalignments of the mask would allow sputtering of the copper and roughening of the surface of the metal lines.